diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-05-01 15:47:06 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-05-01 18:07:32 +0100 |
| commit | 7ac365467ebfe35eb375d0968a73e5ae3cb06ab4 (patch) | |
| tree | d49b3889f2a3f480a3475e44b0d9398eb53bd7fc | |
| parent | 3daac68a5a66844dc969271a9d4a75fce3f6c397 (diff) | |
Platforms/AMD/Styx/MemoryInitPeiLib: use lowest 4 GB of DRAM onlystyx-iommu
For optimal interoperability with PCI masters that are only 32-bit DMA
capable, restrict UEFI to use only the lowest 4 GB of DRAM, which is
the region we can map for 32-bit PCI DMA. This way, there is never a
need to use bounce buffers for streaming DMA (which is otherwise almost
guaranteed, given that UEFI positions itself as high up in memory as it
can)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
| -rw-r--r-- | Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c | 41 | ||||
| -rw-r--r-- | Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf | 1 |
2 files changed, 36 insertions, 6 deletions
diff --git a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c index 9a011b0..fbcf8b9 100644 --- a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c +++ b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -33,6 +33,9 @@ BuildMemoryTypeInformationHob ( VOID
);
+STATIC UINT64 mRealSystemMemorySize;
+STATIC UINT64 mCappedSystemMemorySize;
+
STATIC ARM_MEMORY_REGION_DESCRIPTOR mMemoryTable[] = {
{
// Mapped I/O space
@@ -89,7 +92,7 @@ InitMmu ( UINTN TranslationTableSize;
RETURN_STATUS Status;
- mMemoryTable[2].Length = PcdGet64 (PcdSystemMemorySize);
+ mMemoryTable[2].Length = mRealSystemMemorySize;
DEBUG ((DEBUG_INIT,
"Memory Map\n"
@@ -177,15 +180,12 @@ MemoryPeim ( {
UINT64 Base, Size;
- // Ensure PcdSystemMemorySize has been set
- ASSERT (PcdGet64 (PcdSystemMemorySize) != 0);
-
//
// Now, the permanent memory has been installed, we can call AllocatePages()
//
- Base = PcdGet64 (PcdSystemMemoryBase);
- Size = PcdGet64 (PcdSystemMemorySize);
+ Base = FixedPcdGet64 (PcdSystemMemoryBase);
+ Size = mCappedSystemMemorySize;
if (FixedPcdGetBool (PcdTrustedFWSupport)) {
//
@@ -230,6 +230,20 @@ MemoryPeim ( Size
);
+ if (mRealSystemMemorySize > mCappedSystemMemorySize) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ( EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED ),
+ FixedPcdGet64 (PcdSystemMemoryBase) + SIZE_4GB,
+ mRealSystemMemorySize - mCappedSystemMemorySize
+ );
+ }
+
// Build Memory Allocation Hob
InitMmu ();
@@ -242,3 +256,18 @@ MemoryPeim ( return EFI_SUCCESS;
}
+
+RETURN_STATUS
+EFIAPI
+AmdStyxMemoryInitPeiLibConstructor (
+ VOID
+ )
+{
+ // Ensure PcdSystemMemorySize has been set
+ ASSERT (PcdGet64 (PcdSystemMemorySize) != 0);
+
+ mRealSystemMemorySize = PcdGet64 (PcdSystemMemorySize);
+ mCappedSystemMemorySize = MIN (mRealSystemMemorySize, SIZE_4GB);
+
+ return PcdSet64S (PcdSystemMemorySize, mCappedSystemMemorySize);
+}
diff --git a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf index 10ec28b..8008f48 100644 --- a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf +++ b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -24,6 +24,7 @@ MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM
+ CONSTRUCTOR = AmdStyxMemoryInitPeiLibConstructor
[Sources]
MemoryInitPeiLib.c
|