diff options
| author | Ye Li <ye.li@nxp.com> | 2018-12-20 23:11:51 -0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-12-20 23:54:07 -0800 |
| commit | 5da847a4fad5d85aab497c78a6008cd94b750b35 (patch) | |
| tree | f244958fa82d28a0448a0d9fbdb11ccbc5a3db36 | |
| parent | b053775c03629d4b96e865ce66db89ebce643e91 (diff) | |
MLK-20635 imx8: clock: Fix GPR settings for FEC
FEC has some clock settings inside DSC GPR. Kernel configures them,
but u-boot not. So when doing partition reset, the GPR keeps the value
from kernel, and cause clock issue to u-boot FEC: kernel enables the
divclk in GPR and set the clock slice to 250Mhz, u-boot configures the
clock slice to 125Mhz, the divclk causes the RGMII TX CLK to 62.5Mhz.
Fix the issue by aligning the GPR and clock slice settings with kernel
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit ab6b18bcf3cade15586839274bfde2030726ad37)
| -rw-r--r-- | arch/arm/mach-imx/imx8/clock.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index 78b53f2816..98e06513d3 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -403,8 +403,10 @@ void init_clk_fec(int index) return; } - /* Set SC_R_ENET_0 clock root to 125 MHz */ - rate = 125000000; + /* Set SC_R_ENET_0 clock root to 250 MHz, the clkdiv is set to div 2 + * so finally RGMII TX clk is 125Mhz + */ + rate = 250000000; /* div = 8 clk_source = PLL_1 ss_slice #7 in verfication codes */ err = sc_pm_set_clock_rate(ipc, enet[index], 2, &rate); @@ -422,6 +424,14 @@ void init_clk_fec(int index) return; } + /* Configure GPR regisers */ + sc_misc_set_control(ipc, enet[index], SC_C_TXCLK, 0); + sc_misc_set_control(ipc, enet[index], SC_C_CLKDIV, 1); /* Enable divclk */ + sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_50, 1); + sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_125, 1); + sc_misc_set_control(ipc, enet[index], SC_C_SEL_125, 0); + sc_misc_set_control(ipc, enet[index], SC_C_IPG_STOP, 0); + LPCG_AllClockOn(ENET_0_LPCG + index * 0x10000); } |